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1 IR3871MPBF features ? input voltage range: 3v to 26v ? output voltage range: 0.5v to 12v ? continuous 8a load capability ? constant on - time control ? excellent efficiency at very low output current levels ? compensation loop not required ? programmable switching frequency, soft start, and over current protection ? power good output ? precision voltage reference (0.5v, +/ - 1%) ? pre - bias start up ? under/over voltage fault protection ? ultra small, low profile 5 x 6mm qfn package applications ? notebook and desktop computers ? game consoles ? consumer electronics C stb, lcd, tv, printers ? general purpose pol dc - dc converters description the ir 3871 supirbuck tm is an easy - to - use, fully integrated and highly efficient dc/dc voltage regulator . the onboard constant on time hysteretic controller and mosfets make ir 3871 a space - efficient solution that delivers up to 8 a of precisely controlled output voltage in 60 c ambient temperature applications without airflow . programmable switching frequency, soft start, and over current protection allows for a very flexible solution suitable for many different applications and an ideal choice for battery powered applications . additional features include pre - bias startup, very precise 0 . 5 v reference, over/under voltage shut down, power good output, and enable input with voltage monitoring capability . 8a highly integrated wide - input voltage, synchronous buck regulator sup ir buck tm pd - 97472
2 IR3871MPBF absolute maximum ratings (voltages referenced to gnd unless otherwise specified) ? vin. ff ... - 0.3v to 30v ? vcc, pgood, en ......... - 0.3v to 8.0v ? boot ........ - 0.3v to 40v ? phase ....... - 0.3v to 30v(dc), - 5v(100ns) ? boot to phase ...... - 0.3v to 8v ? iset .... - 0.3v to 30v ? pgnd to gnd ....... - 0.3v to +0.3v ? all other pins ...... - 0.3v to 3.9v ? storage temperature range ................................... - 65 c to 150 c ? junction temperature range ................................... - 40 c to 150 c ? esd classification . jedec class 1c ? moisture sensitivity level ...... jedec level 2 @ 260 c (note 2) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. package information 5mm x 6mm power qfn ordering information pkg desig package description pin count parts per reel m ir3871mtrpbf 17 4000 m ir3871mtr1pbf 17 750 w / c 2 w / c 35 o pcb j o ja = = -
3 IR3871MPBF simplified block diagram
4 IR3871MPBF pin description name number i/o level description nc 1 ----- no connection. iset 2 connecting resistor to phase pin sets over current trip point. pgood 3 5v power good open drain output C pull up with a resistor to 3.3v. gnd 4,17 reference bias return and signal reference. fb 5 3.3v inverting input to pwm comparator, ovp / pgood sense. ss 6 3.3v soft start/shutdown. this pin provides user programmable soft - start function. connect an external capacitor from this pin to gnd to set the startup time of the output voltage. the converter can be shutdown by pulling this pin below 0.3v. nc 7 ----- no connection. 3vcbp 8 3.3v ldo output. a minimum of 1.0 f ceramic capacitor is required from 3vcbp to gnd. nc 9 ----- no connection. vcc 10 5v gate drive supply. a minimum of 1.0f ceramic capacitor must be connected from this pin to the power return (pgnd). pgnd 11 reference power return. phase 12 vin phase node (or switching node) of mosfet half bridge. vin 13 vin input voltage for the system. boot 14 vin +vcc bootstrapped gate drive supply C connect a capacitor to phase. ff 15 vin input voltage feed forward C sets on - time with a resistor to vin. en 16 5v enable pin to turn on and off the device. use two external resistors to set the turn on threshold (see electrical specifications ) for input voltage monitoring.
5 IR3871MPBF recommended operating conditions electrical specifications unless otherwise specified, these specification apply over vin = 12v, vcc = 5v, 0 o c t j 125 o c. * phase pin must not exceed 30v. symbol definition min max unit vin input voltage 3 26* v vcc supply voltage 4.5 7.5 v out output voltage 0.5 12 i out output current 0 8 a fs switching frequency n/a 1000 khz t j junction temperature 0 125 o c parameter note test condition min typ max unit bias supplies vcc turn - on threshold 3.9 4.2 4.5 v vcc turn - off threshold 3.6 3.9 4.2 v vcc threshold hysteresis 150 mv vcc operating current r ff = 200k, en = high, fs = 300khz 7.1 ma vcc shutdown current en = low 35 50 a ff shutdown current en = low 2 a vin shutdown current en = low 1 a internal ldo output ldo output voltage range c 3vcbp = 1 f 3.1 3.3 3.5 v output current 8 ma control loop reference accuracy, v ref v ref 0.495 0.5 0.505 v on - time accuracy r ff = 180k, t j = 65 o c 280 300 320 ns min off time 1 400 ns soft - start current en = high 8 10 12 a zero current threshold 1 measure at v phase - 5 - 2.4 0 mv fault protection iset pin output current 18 20 22 a under voltage threshold falling v fb & monitor pgood 0.37 0.4 0.43 v under voltage hysteresis 1 rising v fb 10 mv over voltage threshold rising v fb & monitor pgood 0.58 0.62 0.66 v over voltage hysteresis 1 falling v fb 10 mv pgood delay threshold (v ss ) 1 v
6 IR3871MPBF electrical specifications (continued) unless otherwise specified, these specification apply over vin = 12v, vcc = 5v, 0 o c t j 125 o c. parameter note test condition min typ max unit gate drive dead time 1 monitor body diode conduction on phase pin 5 30 ns bootstrap pfet forward voltage i(boot) = 10ma 100 200 300 mv upper mosfet static drain - to - source on - resistance vcc = 5v, i d = 7a, t j = 25 o c 14.5 20.8 25.5 m lower mosfet static drain - to - source on - resistance vcc = 5v, i d = 9a, t j = 25 o c 8 10 12.5 m logic input and output en high logic level 2 - - v en low logic level - - 0.6 v en input current en = 3.3v 11 a pgood pull down resistance 25 50 note 1: guaranteed by design, not tested in production note 2: upgrade to industrial/msl2 level applies from date codes 1227 (marking explained on application note an1132 page 2). products with prior date code of 1227 are qualified with msl3 for consumer market.
7 IR3871MPBF typical operating data tested with demoboard shown in figure 7, vin = 12v, vcc = 5v, vout = 1.05v, fs = 300khz, ta = 25 o c, no airflow, unless otherwise specified figure 3. switching frequency vs. output current figure 1. efficiency vs. output current for v out = 1.05v figure 2. efficiency vs. output current for vin = 12v figure 4. frequency vs. r ff figure 5. output voltage regulation vs. output current figure 6. output voltage regulation vs. input voltage at i out = 8a 35% 45% 55% 65% 75% 85% 95% 0.01 0.1 1 10 output current (a) efficiency eff @ 19v in eff @ 12v in eff @ 8v in 1.048 1.049 1.050 1.051 1.052 0 1 2 3 4 5 6 7 8 output current (a) output voltage (v) v out @ 19v in v out @ 12v in v out @ 8v in 0 50 100 150 200 250 300 350 0 1 2 3 4 5 6 7 8 output current (a) frequency (khz) 1.048 1.049 1.050 1.051 1.052 6 8 10 12 14 16 18 20 input voltage (v) output voltage (v) 0 200 400 600 800 1000 1200 200 400 600 800 1000 frequency (khz) rff (kohm) 5.0 vout 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 40% 50% 60% 70% 80% 90% 100% 0.01 0.1 1 10 output current (a) efficiency eff @ 3.3v out , l = 3.3 h eff @ 1.5v out , l = 2.2 h eff @ 1.05v out, l = 1.5 h
8 IR3871MPBF typical application circuit demoboard schematic: vout = 1.05v, fs = 300khz demoboard bill of materials figure 7. typical application circuit for v out = 1.05v, fs = 300khz v out t p7 t p10 en r9 0 v cc t p23 +v sws t p24 +v sws +v i ns r12 op en c26 op en t p8 v outs 1 3 4 5 2 t p21 -vs ws t p25 -vi n1s c27 op en t p12 v sws 1 3 4 5 2 t p22 +v sws v in c7 op en c8 op en c9 33 0uf c10 47 uf -vo ut1 s c11 op en -vd d2s -vd d1s c1 1u f r7 2.80k r8 2.55k c12 0.1uf c24 op en ise t -vo ut1 s +v dd2 s v out +v dd1 s +3 .3v +v i n1s t p6 p gnds t p14 +3 .3v ir3871 u1 ir3 871 3v 3b p 8 nc 1 ss 6 p good 3 ff 15 gnd1 4 fb 5 gnd 17 nc1 7 ise t 2 b oot 14 v in 13 v cc 10 nc2 9 p gnd 11 p ha se 12 en 16 c4 0.22u f v cc s w1 e n / fccm 1 2 4 3 t p4 en t p17 p gnd c20 0.1uf t p26 a gnd c5 op en v sw c21 1u f t p11 p good l1 1.5uh r6 op en c22 op en t p1 v ins r4 10 .5k r3 20 0k c13 op en c2 22 uf c16 op en + c3 68 uf t p2 v in t p5 p gnd c14 op en c17 op en c18 op en t p16 v cc r10 op en fb r5 10 k c15 op en c6 op en t p18 v olt a ge s e ns e +v i ns 1 +v dd1 s 2 +v dd2 s 3 +v out1s 4 +v out2s 5 -vo ut2 s 10 -vd d2s 8 -vo ut1 s 9 -vi ns 6 -vd d1s 7 -vo ut1 s t p9 +v out1s r1 op en fccm p good +v i n1s t p20 +v i n1s +3 .3v c25 1u f +v dd1 s -vd d1s r13 op en +3 .3v t p15 -vo ut1 s r14 op en t p19 fb r11 op en t p13 ss v sw +v dd2 s t p3 fccm ss -vd d2s r2 10 k c19 op en -vi ns p gnd v out c23 op en quantity reference value description manufacturer part-number 1 c4 0.22uf cap,cer,0.22uf,50v,10%,x7r,0603 murata electronics grm188r71h224ka64d 3 c1, c21, c25 1uf cap,cer,1.0uf,25v,x7r,0603 murata electronics grm188r71e105ka12d 1 c2 22uf cap,22uf,25v,ceramic,x5r,1210 panasonic ecj-4yb1e226m 1 c3 68uf cap,68uf,25v,elect,fk,smd panasonic eev-fk1e680p 1 c9 330uf poscap, 330uf, 2.5v, smd sanyo 2r5tpe330m9 1 c10 47uf cap,cer,47uf,6.3v,x5r,0805 tdk c2012x5r0j476m 2 c12, c20 0.1uf cap,cer,0.1uf,50v,10%,x7r,0603 tdk c1608x7r1h104k 1 l1 1.5uh inductor, 1.5uh, 11a, 6.7mohm,smd cyntec pcmb065t-1r5ms 2 r2, r5 10k res,10.0k,ohm,1/10w,1%,0603,smd vishay/dale crcw060310k0fkea 1 r9 0 res,0.0,ohm,1/10w,1%,0603,smd vishay/dale crcw06030000z0eahp 1 r3 200k res,200k,ohm,1/10w,1%,0603,smd vishay/dale crcw0603200kfkea 1 r4 10.5k res,10.5k,ohm,1/10w,1%,0603,smd vishay/dale crcw060310k5fkea 1 r7 2.8k res,2.8k,ohm,1/10w,1%,0603,smd vishay/dale crcw06032k80fkea 1 r8 2.55k res,2.55k,ohm,1/10w,1%,0603,smd vishay/dale crcw06032k55fkea 1 sw1 spst switch, dip, spst, smt c&k components sd02h0sk 1 u1 ir3871 5mm x 6mm qfn ir IR3871MPBF
9 IR3871MPBF figure 8: startup figure 9: shutdown figure 10: dcm (i out = 0.1a) figure 11: ccm (i out = 6a) figure 12: over current protection (tested by shorting vout to pgnd) figure 13: over voltage protection (tested by shorting fb to v out ) en pgood ss vout en pgood ss vout vout phase i l vout phase i l pgood vout iout pgood fb vout i l typical operating data tested with demoboard shown in figure 7, vin = 12v, vcc = 5v, vout = 1.05v, fs = 300khz, t a = 25 o c, no airflow, unless otherwise specified 5v/div 5v/div 1v/div 500mv/div 5ms/div 5v/div 5v/div 1v/div 500mv/div 200 s/div 20mv/div 5v/div 2a/div 10 s/div 20mv/div 5v/div 5a/div 2 s/div 5v/div 1v/div 500mv/div 2a/div 50 s/div 5v/div 1v/div 1v/div 10a/div 1ms/div ss
10 IR3871MPBF figure 14: load transient 0 - 4a figure 15: load transient 4 - 8a figure 16: thermal image at vin = 12v, i out = 8a (ir3871: 66 o c, inductor: 58 o c, pcb: 40 o c) vout phase i l vout phase i l 50mv/div 10v/div 2a/div 20 s/div 50mv/div 10v/div 2a/div 20 s/div figure 17: thermal image at vin = 19v, i out = 8a (ir3871: 71 o c, inductor: 59 o c, pcb: 44 o c) typical operating data tested with demoboard shown in figure 7, vin = 12v, vcc = 5v, vout = 1.05v, fs = 300khz, t a = 25 o c, no airflow, unless otherwise specified
11 IR3871MPBF pwm comparator the pwm comparator initiates a set signal (pwm pulse) when the fb pin falls below the reference (vref) or the soft start (ss) voltage . on - time generator the pwm on - time duration is programmed with an external resistor (r ff ) from the input supply (vin) to the ff pin . the simplified calculation for r ff is shown in equation 1 . the ff pin is held to an internal reference after en goes high . a copy of the current in r ff charges a timing capacitor, which sets the on - time duration, as shown in equation 2 . control logic the control logic monitors input power sources, sequences the converter through the soft - start and protective modes, and initiates an internal run signal when all conditions are met. vcc and 3vcbp pins are continuously monitored, and the ir3871 will be disabled if the voltage of either pin drops below the falling thresholds. en_delay will become high when vcc and 3vcbp are in the normal operating range and the en pin = high. soft start with en = high, an internal 10 a current source charges the external capacitor (c ss ) on the ss pin to set the output voltage slew rate during the soft start interval . the soft start time (t ss ) can be calculated from equation 3 . the feedback voltage tracks the ss pin until ss reaches the 0 . 5 v reference voltage (vref), then feedback is regulated to vref . c ss will continue to be charged, and when ss pin reaches v ss (see electrical specification ), ss_delay goes high . with en_delay = low, the capacitor voltage and ss pin is held to the fb pin voltage . a normal startup sequence is shown in figure 18 . circuit description figure 18. normal startup pgood the pgood pin is open drain and it needs to be externally pulled high . high state indicates that output is in regulation . the pgood logic monitors en_delay, ss_delay, and under/over voltage fault signals . pgood is released only when en_delay and ss_delay = high and output voltage is within the ov and uv thresholds . pre - bias startup ir 3871 is able to start up into pre - charged output, which prevents oscillation and disturbances of the output voltage . with constant on - time control, the output voltage is compared with the soft start voltage (ss) or vref, depending on which one is lower, and will not start switching unless the output voltage drops below the reference . this scheme prevents discharge of a pre - biased output voltage . shutdown the ir 3871 will shutdown if vcc is below its uvlo limit . the ir 3871 can be shutdown by pulling the en pin below its lower threshold . alternatively, the output can be shutdown by pulling the soft start pin below 0 . 3 v . (2) v 20 1 r t in ff on pf v ? ? ? (1) f 20 1 v r sw out ff ? ? ? pf v (3) a 10 5 . 0 t ss ? v c ss ? ?
12 IR3871MPBF under/over voltage monitor the ir 3871 monitors the voltage at the fb node through a 350 ns filter . if the fb voltage is below the under voltage threshold, uv# is set to low holding pgood to be low . if the fb voltage is above the over voltage threshold, ov# is set to low, the shutdown signal (sd) is set to high, mosfet gates are turned off, and pgood signal is pulled low . toggling vcc or en will allow the next start up . figure 19 shows pgood status change when uv/ov is detected . the over voltage and under voltage thresholds can be found in the electrical specification section . circuit description over current monitor the over - current circuitry monitors the output current during each switching cycle . the voltage across the lower mosfet, vphase, is monitored for over current and zero crossing . the ocp circuit evaluates vphase for an over current condition typically 270 ns after the lower mosfet is gated on . this delay functions to filter out switching noise . the minimum lower gate interval allows time to sample vphase . the over current trip point is programmed with a resistor from the iset pin to phase pin, as shown in equation 4 , where tj is the junction temperature of q 2 at operation conditions, and 0 . 4 is the temperature coefficient (~ 4000 ppm/ ? c) of q 2 r dson . when over current is detected, the output gates are tri - state and ss voltage is pulled to 0 v . this initiates a new soft start cycle . if there is a total of four oc events, the ir 3871 will disable switching, as shown in figure 20 . toggling vcc or en will allow the next start up . figure 20. over current protection figure 19(a). under/over voltage monitor figure 19(b). over voltage protection * typical filter delay (4) 0.4) 100 25 t (1 20 i r r j oc dson set ? ? ? ? ? ? a ?
13 IR3871MPBF circuit description stability considerations constant - on - time control is a fast , ripple based control scheme . unstable operation can occur if certain conditions are not met . the system instability is usually caused by : ? switching noise coupled to fb input . this causes the pwm comparator to trigger prematurely after the 400 ns minimum q 2 on - time . it will result in double or multiple pulses every switching cycle instead of the expected single pulse . double pulsing can causes higher output voltage ripple, but in most application it will not affect operation . this can usually be prevented by careful layout of the ground plane and the fb sensing trace . ? steady state ripple on fb pin being too small . the pwm comparator in ir 3871 requires minimum 7 mvp - p ripple voltage to operate stably . not enough ripple will result in similar double pulsing issue described above . solving this may require using output capacitors with higher esr . ? esr loop instability . the stability criteria of constant on - time is : esr*cout>ton/ 2 . if esr is too small that this criteria is violated then sub - harmonic oscillation will occur . this is similar to the instability problem of peak - current - mode control with d> 0 . 5 . increasing esr is the most effective way to stabilize the system, but the price paid is the larger output voltage ripple . ? for applications with all ceramic output capacitors, the esr is usually too small to meet the stability criteria . in these applications, external slope compensation is necessary to make the loop stable . the ramp injection circuit, composed of r 6 , c 13 , and c 14 , shown in figure 7 is required . the inductor current ripple sensed by r 6 and c 13 is ac coupled to the fb pin through c 14 . c 14 is usually chosen between 1 to 10 nf, and c 13 between 10 to 100 nf . r 6 should then be chosen such that l/dcr = c 13 *r 6 . gate drive logic the gate drive logic features adaptive dead time, diode emulation, and a minimum lower gate interval . an adaptive dead time prevents the simultaneous conduction of the upper and lower mosfets . the lower gate voltage (lgate) must be below approximately 1 v after pwm goes high before the upper mosfet can be gated on . also, the upper gate voltage (ugate), the difference voltage between ugate and phase, must be below approximately 1 v after pwm goes low before the lower mosfet can be gated on . the control mosfet is gated on after the adaptive delay for pwm = high and the synchronous mosfet is gated on after the adaptive delay for pwm = low . the lower mosfet is driven off when the signal zcross indicates that the inductor current has reversed as detected by the phase voltage crossing the zero current threshold . the synchronous mosfet stays off until the next pwm falling edge . when the lower peak of inductor current is above zero, a forced continuous current condition is selected . the control mosfet is gated on after the adaptive delay for pwm = high, and the synchronous mosfet is gated on after the adaptive delay for pwm = low . the synchronous mosfet gate is driven on for a minimum duration . this minimum duration allows time to recharge the bootstrap capacitor and allows the current monitor to sample the phase voltage .
14 IR3871MPBF input capacitor selection the main function of the input capacitor bank is to provide the input ripple current and fast slew rate current during the load current step up . the input capacitor bank must have adequate ripple current carrying capability to handle the total rms current . figure 21 shows a typical input current . equation 6 shows the rms input current . the rms input current contains the dc load current and the inductor ripple current . as shown in equation 5 , the inductor ripple current is unrelated to the load current . the maximum rms input current occurs at the maximum output current . the maximum power dissipation in the input capacitor equals the square of the maximum rms input current times the input capacitors total esr . figure 21. typical input current waveform. component selection selection of components for the converter is an iterative process which involves meeting the specifications and trade - offs between performance and cost . the following sections will guide one through the process . inductor selection inductor selection involves meeting the steady state output ripple requirement, minimizing the switching loss of upper mosfets, meeting transient response specifications and minimizing the output capacitance . the output voltage includes a dc voltage and a small ac ripple component due to the low pass filter which has incomplete attenuation of the switching harmonics . neglecting the inductance in series with the output capacitor, the magnitude of the ac voltage ripple is determined by the total inductor ripple current flowing through the total equivalent series resistance (esr) of the output capacitor bank . the voltage rating of the input capacitor needs to be greater than the maximum input voltage because of high frequency ringing at the phase node . the typical percentage is 25 % . one can use equation 5 to find the required inductance . i is defined as shown in figure 21 . the main advantage of small inductance is increased inductor current slew rate during a load transient, which leads to a smaller output capacitance requirement as discussed in the output capacitor selection section . the draw back of using smaller inductances is increased switching power loss in upper mosfet, which reduces the system efficiency and increases the thermal dissipation . ? ? (5) l 2 v v t i out in on ? ? ? ? i n p u t c u r r e n t i i o u t t s ? ? (6) i i 3 1 1 fs ton i dt t f ts 1 i 2 out out ts 0 2 in_rms ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
15 IR3871MPBF boot capacitor selection the boot capacitor starts the cycle fully charged to a voltage of vb( 0 ) . cg equals 0 . 65 nf in ir 3871 . choose a sufficiently small v such that vb( 0 ) - v exceeds the maximum gate threshold voltage to turn on the high side mosfet . choose a boot capacitor value larger than the calculated c boot in equation 9 . equation 9 is based on charge balance at ccm operation . usually the boot capacitor will be discharged to a much lower voltage when the circuit is operating in dcm mode at light load, due to much longer q 2 off time and the bias current drawn by the ic . boot capacitance needs to be increased if insufficient turn - on of q 1 is observed at light load, typically larger than 0 . 1 f is needed . the voltage rating of this part needs to be larger than vb( 0 ) plus the desired derating voltage . its esr and esl needs to be low in order to allow it to deliver the large current and di/dts which drive mosfets most efficiently . in support of these requirements a ceramic capacitor should be chosen . output capacitor selection selection of the output capacitor requires meeting voltage overshoot requirements during load removal, and meeting steady state output ripple voltage requirements . the output capacitor is the most expensive converter component and increases the overall system cost . the output capacitor decoupling in the converter typically includes the low frequency capacitor, such as specialty polymer aluminum, and mid frequency ceramic capacitors . the first purpose of output capacitors is to provide current when the load demand exceeds the inductor current, as shown in figure 22 . equation 7 shows the charge requirement for a certain load . the advantage provided by the ir 3871 at a load step is to reduce the delay compared to a fixed frequency control method (in microseconds or ( 1 - d)*ts) . if the load increases right after the pwm signal goes low, the longest delay will be equal to the minimum lower gate on as shown in the electrical specification table . the ir 3871 also reduces the inductor current slew time, the time it takes for the inductor current to reach equality with the output current, by increasing the switching frequency up to 2 . 5 mhz . the result reduces the recovery time . the second purpose of the output capacitor is to minimize the overshoot of the output voltage when the load decreases as shown in figure 23 . by using the law of energy before and after the load removal, equation 8 shows the output capacitance requirement for a load step . figure 22. charge requirement during load step the output voltage drop, vdrop, initially depends on the characteristic of the output capacitor . vdrop is the sum of the equivalent series inductance (esl) of the output capacitor times the rate of change of the output current and the esr times the change of the output current . vesr is usually much greater than vesl . the ir 3871 requires a total esr such that the ripple voltage at the fb pin is greater than 7 mv . figure 23. typical output voltage response waveform. component selection ? ? (7b) v v istep l 2 1 v 1 c (7a) t istep 0.5 v c q out in drop out 2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? t l o a d c u r r e n t i s t e p i n d u c t o r s l e w r a t e o u t p u t c h a r g e t (8) v v i l c 2 out 2 os 2 step out ? ? ? i o u t i s t e p v o u t v l v e s r v o s v d r o p (9) 1 v (0) v c c b g boot ? ? ? ? ? ? ? ? ?
16 IR3871MPBF design criteria : input voltage, vin, = 6v to 21v output voltage, vout = 1.25v switching frequency, fs = 400khz inductor ripple current, 2i = 3a maximum output current, iout = 6a over current trip, ioc = 9a overshoot allowance, vos = vout + 50mv undershoot allowance, vdrop = 50mv choose an input capacitor : find r ff : choose an inductor with the lowest dcr and ac power loss as possible to increase the overall system efficiency . for instance, choose an fdu 0650 - r 82 m manufactured by toko . the inductance of this part is 820 nh and has 4 . 2 m dcr . ripple current needs to be recalculated using the chosen inductor . a panasonic 10 f (ecj 3 yb 1 e 106 m) accommodates 6 arms of ripple current at 300 khz . due to the chemistry of multilayer ceramic capacitors, the capacitance varies over temperature and operating voltage, both ac and dc . one 10 f capacitor is recommended . in a practical solution, one 1 f capacitor is required along with 10 f . the purpose of the 1 f capacitor is to suppress the switching noise and deliver high frequency current . choose an output capacitor : to meet the undershoot specification, select a set of output capacitors which has an equivalent esr of 10 m ( 50 mv/ 5 a) . to meet the overshoot specification, equation 8 will be used to calculate the minimum output capacitance . as a result, 160 f will be needed for 5 a load remover . combine those two requirements, one can choose a set of output capacitors from manufactures such as sp - cap (specialty polymer capacitor) from panasonic or poscap from sanyo . a 150 f (eefsl 0 d 151 r) from panasonic is recommended . this capacitor has 9 m esr which leaves margin for the voltage drop of the esl during load step up . the typical esl for this capacitor is around 2 nh . pick a standard value 158 k, 1% resistor. find r set : the r dson of the lower mosfet could be expected to increase by a factor of 1 . 4 over temperature . therefore, pick a 6 . 49 k, 1 % standard resistor . find a resistive voltage divider for v out = 1 . 25 v : choose the soft start capacitor : once the soft start time has chosen, such as 1000 us to reach to the reference voltage, a 22 nf for c ss is used to meet 1000 s . choose an inductor to meet the design specification : r 2 = 1 . 33 k , r 1 = 1 . 96 k, both 1 % standard resistors . design example a a a v v a 1.5 6 1.75 3 1 1 21 1.25 6 i 2 in_rms ? ? ? ? ? ? ? ? ? ? ? ? k 156 400k 20 1 1.25 r ff ? ? ? ? ? hz pf v v ? ? ? ? ? ? k 6.3 20 9 10m 1.4 r set a a ? ? ? ? ? h hz a v v v v i ? 1.0 400k 3 21 1.25 - 21 1.25 f 2 v v v v l s in out in out ? ? ? ? ? ? ? ? ? ? ? ? a hz h v v v v 1.75 400k 0.82 21 2 1.25 - 21 1.25 i ? ? ? ? ? ? ? v 0.5 v r r r v out 1 2 2 fb ? ? ? ?
17 IR3871MPBF bypass capacitor : one 1 f high quality ceramic capacitor should be placed as near vcc pin as possible . the other end of capacitor can be connected to a via or connected directly to gnd plane . use a gnd plane instead of a thin trace to the gnd pin because a thin trace have too much impedance . boot circuit : c boot should be placed near the boot and phase pins to reduce the impedance when the upper mosfet turns on . power stage : figure 24 shows the current paths and their directions for the on and off periods . the on time path has low average dc current and high ac current . therefore, it is recommended to place the input ceramic capacitor, upper, and lower mosfet in a tight loop as shown in figure 24 . the purpose of the tight loop from the input ceramic capacitor is to suppress the high frequency ( 10 mhz range) switching noise and reduce electromagnetic interference (emi) . if this path has high inductance, the circuit will cause voltage spikes and ringing, and increase the switching loss . the off time path has low ac and high average dc current . therefore, it should be laid out with a tight loop and wide trace at both ends of the inductor . lowering the loop resistance reduces the power loss . the typical resistance value of 1 - ounce copper thickness is 0 . 5 m per square inch . figure 24. current path of power stage layout recommendation q1 q2 v o u t v i n o n o f f c o u t c i n i r 3 8 7 1
18 IR3871MPBF pcb metal and components placement lead lands (the 13 ic pins) width should be equal to nominal part lead width . the minimum lead to lead spacing should be 0 . 2 mm to minimize shorting . lead land length should be equal to maximum part lead length + 0 . 3 mm outboard extension . the outboard extension ensures a large toe fillet that can be easily inspected . pad lands (the 4 big pads) length and width should be equal to maximum part pad length and width . however, the minimum metal to metal spacing should be no less than ; 0 . 17 mm for 2 oz . copper or no less than 0 . 1 mm for 1 oz . copper or no less than 0 . 23 mm for 3 oz . copper .
19 IR3871MPBF solder resist it is recommended that the lead lands are non solder mask defined (nsmd) . the solder resist should be pulled away from the metal lead lands by a minimum of 0 . 025 mm to ensure nsmd pads . the land pad should be solder mask defined (smd), with a minimum overlap of the solder resist onto the copper of 0 . 05 mm to accommodate solder resist misalignment . ensure that the solder resist in between the lead lands and the pad land is 0 . 15 mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land .
20 IR3871MPBF stencil design the stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. reducing the amount of solder deposited will minimize the occurrences of lead shorts. if too much solder is deposited on the center pad the part will float and the lead lands will open. the maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back in order to decrease the risk of shorting the center land to the lead lands when the part is pushed into the solder paste.
21 IR3871MPBF ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252 - 7105 tac fax: (310) 252 - 7903 this product has been designed and qualified for the industrial market (note 2) visit us at www.irf.com for sales contact information data and specifications subject to change without notice. 03/12 min max min max min max min max a 0.8 1 0.0315 0.0394 l 0.35 0.45 0.0138 0.0177 a1 0 0.05 0 0.002 m 2.441 2.541 0.0962 0.1001 b 0.375 0.475 0.1477 0.1871 n 0.703 0.803 0.0277 0.0314 b1 0.25 0.35 0.0098 0.1379 o 2.079 2.179 0.0819 0.0858 c p 3.242 3.342 0.1276 0.1316 d q 1.265 1.365 0.0498 0.05374 e r 2.644 2.744 0.1042 0.1081 e s 1.5 1.6 0.0591 0.063 e1 t1, t2, t3 e2 t4 t5 dim milimiters inches dim milimiters inches 0.203 ref. 0.008 ref. 5.000 basic 1.970 basic 6.000 basic 2.364 basic 1.033 basic 0.0407 basic 0.650 basic 0.0256 basic 0.852 basic 0.0259 basic 1.153 basic 0.045 basic 0.727 basic 0.0286 basic 0.401 basic 0.016 bacis

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